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dual supply octal translating transceiver with 3state outputs the 74lvx4245 is a 24pin dualsupply, octal translating transceiver that is designed to interface between a 5v bus and a 3v bus in a mixed 3v/5v supply environment such as laptop computers using a 3.3v cpu and 5v lcd display. the a port interfaces with the 5v bus; the b port interfaces with the 3v bus. the transmit/receive (t/r ) input determines the direction of data flow. transmit (activehigh) enables data from the a port to the b port. receive (activelow) enables data from the b port to the a port. the output enable (oe ) input, when high, disables both a and b ports by placing them in 3state. ? bidirectional interface between 5v and 3v buses ? control inputs compatible with ttl level ? 5v data flow at a port and 3v data flow at b port ? outputs source/sink 24ma at 5v bus and 12ma at 3v bus ? guaranteed simultaneous switching noise level and dynamic threshold performance ? available in soic and tssop packages ? functionally compatible with the 74 series 245 figure 1. 24lead pinout (top view) 23 24 22 21 20 19 18 2 1 34567 v ccb 17 8 16 9 15 10 v ccb oe b0 b1 b2 b3 b4 b5 b6 v cca t/r a0 a1 a2 a3 a4 a5 a6 a7 14 11 13 12 b7 gnd gnd gnd mc74lvx4245 pin names function output enable input transmit/receive input side a 3state inputs or 3state outputs side b 3state inputs or 3state outputs pins oe t/r a0a7 b0b7 dw suffix 24lead plastic soic package case 751e04 dt suffix 24lead plastic tssop package case 948h01 lvx lowvoltage cmos ? semiconductor components industries, llc, 2001 january, 2001 rev. 3 1 publication order number: mc74lvx4245/d
mc74lvx4245 http://onsemi.com 2 b0 oe 22 t/r 2 a0 b1 a1 b2 a2 b3 a3 b4 a4 b5 a5 b6 a6 b7 a7 figure 2. logic diagram 3 4 5 6 7 8 9 10 21 20 19 18 17 16 15 14 inputs operating mode oe t/r operating mode noninverting l l b data to a bus l h a data to b bus h x z h = high voltage level; l = low v oltage level; z = high impedance state; x = high or low voltage level and transitions are acceptable; for i cc reasons, do not float inputs
mc74lvx4245 http://onsemi.com 3 absolute maximum ratings* symbol parameter value condition unit v cca , v ccb dc supply voltage 0.5 to +7.0 v v i dc input voltage oe , t/r 0.5 to v cca +0.5 v v i/o dc input/output voltage an 0.5 to v cca +0.5 v bn 0.5 to v ccb +0.5 v i ik dc input diode current oe , t/r 20 v i < gnd ma i ok dc output diode current 50 v o < gnd; v o > v cc ma i o dc output source/sink current 50 ma i cc , i gnd dc supply current per output pin maximum current at i cca maximum current at i ccb 50 200 100 ma t stg storage temperature range 65 to +150 c latchup dc latchup source/sink current 300 ma * absolute maximum continuous ratings are those values beyond which damage to the device may occur. exposure to these conditions or conditions beyond those indicated may adversely affect device reliability. functional operation under absolutemaximumrated co nditions is not implied. recommended operating conditions symbol parameter min max unit v cca , v ccb supply voltage v cca v ccb 4.5 2.7 5.5 3.6 v v i input voltage oe , t/r 0 v cca v v i/o input/output voltage an bn 0 0 v cca v ccb v t a operating freeair temperature 40 +85 c d t/ d v minimum input edge rate v in from 30% to 70% of v cc ; v cc at 3.0v, 4.5v, 5.5v 0 8 ns/v dc electrical characteristics t a = 25 c t a = 40 to +85 c symbol parameter condition v cca v ccb typ guaranteed limits unit v iha minimum high level itvlt an,oe t/r v out 0.1v or 5.5 4.5 3.3 3.3 2.0 2.0 2.0 2.0 v v ihb input voltage bn or v cc 0.1v 5.0 5.0 3.6 2.7 2.0 2.0 2.0 2.0 v v ila maximum low level itvlt an,oe t/r v out 0.1v or 5.5 4.5 3.3 3.3 0.8 0.8 0.8 0.8 v v ilb input voltage bn or v cc 0.1v 5.0 5.0 2.7 3.6 0.8 0.8 0.8 0.8 v v oha minimum high level ot tvlt i out = 100 m a i oh = 24ma 4.5 4.5 3.0 3.0 4.50 4.25 4.40 3.86 4.40 3.76 v v ohb output voltage i out = 100 m a i oh = 12ma i oh = 8ma 4.5 4.5 4.5 3.0 3.0 2.7 2.99 2.80 2.50 2.9 2.4 2.4 2.9 2.4 2.4 v v ola maximum low level ot tvlt i out = 100 m a i ol = 24ma 4.5 4.5 3.0 3.0 0.002 0.18 0.10 0.36 0.10 0.44 v v olb output voltage i out = 100 m a i ol = 12ma i ol = 8ma 4.5 4.5 4.5 3.0 3.0 2.7 0.002 0.1 0.1 0.10 0.31 0.31 0.10 0.40 0.40 v
mc74lvx4245 http://onsemi.com 4 dc electrical characteristics t a = 40 to +85 c t a = 25 c symbol unit guaranteed limits typ v ccb v cca condition parameter i in max input leakage current oe , t/r v i = v cca , gnd 5.5 3.6 0.1 1.0 m a i oza max 3state out- put leakage an v i = v ih , v il oe = v cca v o = v cca , gnd 5.5 3.6 0.5 5.0 m a i ozb max 3state out- put leakage bn v i = v ih , v il oe = v cca v o = v ccb , gnd 5.5 3.6 0.5 5.0 m a d i cc maximum i cct per input an,oe t/r v i =v cca 2.1v 5.5 3.6 1.0 1.35 1.5 ma bn v i =v ccb 0.6v 5.5 3.6 0.35 0.5 ma i cca quiescent v cca supply current an=v cca or gnd bn=v ccb or gnd oe =gnd t/r =gnd 5.5 3.6 8 80 m a i ccb quiescent v ccb supply current an=v cca or gnd bn=v ccb or gnd oe =gnd t/r =v cca 5.5 3.6 5 50 m a v olpa v olpb quiet output max dynamic v ol notes 1., 2. 5.0 5.0 3.3 3.3 1.5 1.2 v v olva v olvb quiet output min dynamic v ol notes 1., 2. 5.0 5.0 3.3 3.3 1.2 0.8 v v ihda v ihdb min high level dynamic input volt- age notes 1., 3. 5.0 5.0 3.3 3.3 2.0 2.0 v v ilda v ildb max low level dynamic input volt- age notes 1., 3. 5.0 5.0 3.3 3.3 0.8 0.8 v 1. worst case package. 2. max number of outputs defined as (n). data inputs are driven 0v to v cc level; one output at gnd. 3. max number of data inputs (n) switching. (n1) inputs switching 0v to v cc level. input under test switching: v cc level to threshold (v ihd ), 0v to threshold (v ild ), f = 1mhz. capacitive characteristics symbol parameter condition typical unit c in input capacitance v cca = 5.0v; v ccb = 3.3v 4.5 pf c i/o input/output capacitance v cca = 5.0v; v ccb = 3.3v 15 pf c pd power dissipation capacitance b a (measured at 10mhz) a b v cca = 5.0v v ccb = 3.3v 55 40 pf
mc74lvx4245 http://onsemi.com 5 ac electrical characteristics t a = 40 to +85 c c l = 50pf t a = 40 to +85 c c l = 50pf v cca = 5v 0.5v v ccb = 3.3v 0.3v v cca = 5v 0.5v v ccb = 2.7v symbol parameter min typ (note 4.) max min max unit t phl t plh propagation delay a to b 1.0 1.0 5.1 5.3 9.0 9.0 1.0 1.0 10.0 10.0 ns t phl t plh propagation delay b to a 1.0 1.0 5.4 5.5 9.0 9.0 1.0 1.0 10.0 10.0 ns t pzl t pzh output enable time oe to b 1.0 1.0 6.5 6.7 10.5 10.5 1.0 1.0 11.5 11.5 ns t pzl t pzh output enable time oe to a 1.0 1.0 5.2 5.8 9.5 9.5 1.0 1.0 10.0 10.0 ns t phz t plz output disable time oe to b 1.0 1.0 6.0 3.3 10.0 7.0 1.0 1.0 10.0 7.5 ns t phz t plz output disable time oe to a 1.0 1.0 3.9 2.9 7.5 7.0 1.0 1.0 7.5 7.5 ns t oshl t oslh output to output skew, data to output (note 5.) 1.0 1.5 1.5 ns 4. typical values at v cca = 5.0v; v ccb = 3.3v at 25 c. 5. skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of the same d evice. the specification applies to any outputs switching in the same direction, either hightolow (t oshl ) or lowtohigh (t oslh ); parameter guaranteed by design.
mc74lvx4245 http://onsemi.com 6 dual supply octal translating transceiver the 74lvx4245 is a is a dualsupply device well capable of bidirectional signal voltage translation. this level shifting ability provides an excellent interface between low voltage cpu local bus and a standard 5v i/o bus. the device control inputs can be controlled by either the low voltage cpu and core logic or a bus arbitrator with 5v i/o levels. the lvx4245 is ideal for mixed voltage applications such as notebook computers using a 3.3v cpu and 5v peripheral devices. applications: mixed mode dual supply interface solutions the lvx4245 is designed to solve 3v/5v interfaces when cmos devices cannot tolerate i/o levels above their applied v cc . if an i/o pin of a 3v device is driven by a 5v device, the pchannel transistor in the 3v device will conduct e causing current flow from the i/o bus to the 3v power supply. the result may be destruction of the 3v device through latchup effects. a current limiting resistor may be used to prevent destruction, but it causes speed degradation and needless power dissipation. a better solution is provided in the lvx4245. it provides two different output levels that easily handle the dual voltage interface. the a port is a dedicated 5v port; the b port is a dedicated 3v port. no tag on page no tag shows how the lvx4245 may fit into a mixed 3v/5v system. since the lvx4245 is a `245 transceiver, the user may either use it for bidirectional or unidirectional applications. the center 20 pins are configured to match a `245 pinout. this enables the user to easily replace this level shifter with a 3v `245 device without additional layout work or re manufacture of the circuit board (when both buses are 3v). figure 3. 3.3v/5v interface block diagram lvx4245 v ccb v cca lvx4245 v ccb v cca eisa - isa - mca (5v i/o levels) low voltage cpu local bus powering up the lvx4245 when powering up the lvx4245, please note that if the v ccb pin is poweredup well in advance of the v cca pin, several milliamps of either i cca or i ccb current will result. if the v cca pin is poweredup in advance of the v ccb pin then only nanoamps of icc current will result. in actuality the v ccb can be powered aslightlyo before the v cca without the current penalty, but this asetup timeo is dependent on the powerup ramp rate of the v cc pins. with a ramp rate of approximately 50mv/ns (50v/ m s) a 25ns setup time was observed (v ccb before v cca ). with a 7v/ m s rate, the setup time was about 140ns. when all is said and done, the safest powerup strategy is to simply power v cca before v ccb . one more note: if the v ccb ramp rate is faster than the v cca ramp rate then power problems might still occur, even if the v cca powerup began prior to the v ccb powerup.
mc74lvx4245 http://onsemi.com 7 figure 4. mc74lvx4245 fits into a system with 3v subsystem and 5v subsystem keyboard controller super i/o core logic transceivers pcmcia controller vga controller lvx4245 a port a0:7 cache sram cpu 386/486 rom bios memory driver b port b0:7 microchannel/ eisa/isa/at 5v bus local 3v bus 3v 5v 5v v cca 3v v ccb v cca (t/r ) dir a0 a1 a2 a3 a4 a5 a6 a7 gnd gnd v ccb v ccb oe b0 b1 b2 b3 b4 b5 b6 b7 gnd mc74lvx4245 standard 74 series `245 figure 5. mc74lvx4245 pin arrangement is compatible to 20pin 74 series `245s
mc74lvx4245 http://onsemi.com 8 waveform 1 - propagation delays t r = t f = 2.5ns, 10% to 90%; f = 1mhz; t w = 500ns v cc 0v v oh v ol an, bn bn, an t phl t plh waveform 2 - output enable and disable times t r = t f = 2.5ns, 10% to 90%; f = 1mhz; t w = 500ns v cca 0v 0v oe , t/r an, bn t pzh v cc t phz t pzl t plz an, bn 50% v cc 50% v cc 50% v cc 50% v cc 50% v cc 50% v cc figure 6. ac waveforms 50% v cc v cc v oh - 0.3v v ol + 0.3v gnd 50% v cc open pulse generator r t dut v cc r l r 1 c l 2 v cc test switch t plh , t phl , t pzh , t phz open t pzl , t plz 2 v cc c l = 50pf or equivalent (includes jig and probe capacitance) r l = r 1 = 500 w or equivalent r t = z out of pulse generator (typically 50 w ) figure 7. test circuit
mc74lvx4245 http://onsemi.com 9 outline dimensions dt suffix plastic tssop package case 948h01 issue o dim min max min max inches millimeters a 7.70 7.90 0.303 0.311 b 4.30 4.50 0.169 0.177 c --- 1.20 --- 0.047 d 0.05 0.15 0.002 0.006 f 0.50 0.75 0.020 0.030 g 0.65 bsc 0.026 bsc h 0.27 0.37 0.011 0.015 j 0.09 0.20 0.004 0.008 j1 0.09 0.16 0.004 0.006 k 0.19 0.30 0.007 0.012 k1 0.19 0.25 0.007 0.010 l 6.40 bsc 0.252 bsc m 0 8 0 8 notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeter. 3. dimension a does not include mold flash, protrusions or gate burrs. mold flash or gate burrs shall not exceed 0.15 (0.006) per side. 4. dimension b does not include interlead flash or protrusion. interlead flash or protrusion shall not exceed 0.25 (0.010) per side. 5. dimension k does not include dambar protrusion. allowable dambar protrusion shall be 0.08 (0.003) total in excess of the k dimension at maximum material condition. 6. terminal numbers are shown for reference only. 7. dimension a and b are to be determined at datum plane -w-. s u 0.15 (0.006) t 2x l/2 s u m 0.10 (0.004) v s t l u seating plane 0.10 (0.004) t ??? ??? ??? section nn detail e j j1 k k1 detail e f m w 0.25 (0.010) 13 24 12 1 pin 1 ident. h g a d c b s u 0.15 (0.006) t v 24x ref k n n
mc74lvx4245 http://onsemi.com 10 outline dimensions dw suffix plastic soic package case 751e04 issue e t 0.010 (0.25) a b m s s min min max max millimeters inches dim a b c d f g j k m p r 15.25 7.40 2.35 0.35 0.41 0.23 0.13 0 10.05 0.25 15.54 7.60 2.65 0.49 0.90 0.32 0.29 8 10.55 0.75 0.601 0.292 0.093 0.014 0.016 0.009 0.005 0 0.395 0.010 0.612 0.299 0.104 0.019 0.035 0.013 0.011 8 0.415 0.029 1.27 bsc 0.050 bsc notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeter. 3. dimensions a and b do not include mold protrusion. 4. maximum mold protrusion 0.15 (0.006) per side. 5. dimension d does not include dambar protrusion. allowable dambar protrusion shall be 0.13 (0.005) total in excess of d dimension at maximum material condition. a b 112 24 13 t c k seating plane r x 45 g 22 pl p 12 pl 0.010 (0.25) b m m f j m d 24 pl
mc74lvx4245 http://onsemi.com 11 notes
mc74lvx4245 http://onsemi.com 12 on semiconductor and are trademarks of semiconductor components industries, llc (scillc). scillc reserves the right to make changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. atypicalo parameters which may be provided in scill c data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. all operating parameters, including atypicalso must be validated for each customer application by customer's technical experts. scillc does not convey any license under its patent rights nor the rights of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body , or other applications intended to support or sustain life, or for any other application in which the failure of the scillc product could create a sit uation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indemnify and hold scillc and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthori zed use, even if such claim alleges that scillc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. publication ordering information central/south america: spanish phone : 3033087143 (monfri 8:00am to 5:00pm mst) email : onlitspanish@hibbertco.com tollfree from mexico: dial 018002882872 for access then dial 8662979322 asia/pacific : ldc for on semiconductor asia support phone : 3036752121 (tuefri 9:00am to 1:00pm, hong kong time) toll free from hong kong & singapore: 00180044223781 email : onlitasia@hibbertco.com japan : on semiconductor, japan customer focus center 4321 nishigotanda, shinagawaku, tokyo, japan 1410031 phone : 81357402700 email : r14525@onsemi.com on semiconductor website : http://onsemi.com for additional information, please contact your local sales representative. mc74lvx4245/d north america literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 3036752175 or 8003443860 toll free usa/canada fax : 3036752176 or 8003443867 toll free usa/canada email : onlit@hibbertco.com fax response line: 3036752167 or 8003443810 toll free usa/canada n. american technical support : 8002829855 toll free usa/canada europe: ldc for on semiconductor european support german phone : (+1) 3033087140 (monfri 2:30pm to 7:00pm cet) email : onlitgerman@hibbertco.com french phone : (+1) 3033087141 (monfri 2:00pm to 7:00pm cet) email : onlitfrench@hibbertco.com english phone : (+1) 3033087142 (monfri 12:00pm to 5:00pm gmt) email : onlit@hibbertco.com european tollfree access*: 0080044223781 *available from germany, france, italy, uk, ireland

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